The present invention relates generally to digital electronics, and more particularly, to a power-on-reset (POR) circuit that provides a reset signal to a chip when the supply voltage ramps up so that the chip always starts with a known state.
A chip typically is made up of various circuit modules that operate together to provide desired functionality. In many applications, upon power on, a chip requires initialization for the proper operation of the circuits. The initialization is performed once the power supply voltage, referred to as VDD, has ramped up to a voltage exceeding a pre-defined threshold value. The initialization enables the various modules and the clock signals to be reset to predetermined values.
A POR circuit performs such initialization. The POR circuit monitors the power supply voltage level and resets various modules within the chip when the power supply voltage level exceeds a predetermined threshold referred to as the assertion voltage. In particular, the POR circuit provides a reliable reset state on power-up. Such functionality prevents the malfunctioning of the chip due to being initialized in an unknown state.
The assertion voltage of a POR circuit should be independent of the ramp-rate of VDD for reliable start up of the chip. The current drawn from the POR circuit should be as small as possible once the reset signal has been generated. Ideally, the POR circuit should draw zero current once the POR action is complete. Further, the POR circuit should have a minimum re-arm time, i.e., the time between two successive VDD ramp-ups, during which VDD remains at zero voltage, should be as small as possible. This is especially desirable in cases where VDD is switched on and off at a high rate.
Additionally, in applications such as Dynamic Voltage Frequency Scaling (DVFS) and deep sleep mode (DSM), the POR circuit should not generate reset pulses while VDD is dynamically varied, for example, between 1.2V to 0.8V. For such applications, the resetting of the chip leads to system failure. Further, it is desirable that the POR circuit be able to work reliably at low-supply voltages, such as 1.2V for current process technology nodes such as 90 nm and 65 nm.
The conventional POR circuit does not satisfy all of the design constraints mentioned above. In particular, the voltage at which the reset occurs varies with the ramp rate for VDD. The POR circuit also consumes a significant amount of constant DC current even if the POR circuit is inactive, such as after the POR action is complete. This leads to unnecessary power consumption. Further, it is not suitable for DVFS/DSM applications since a reset signal is generated even if VDD is varied dynamically.
Accordingly, there is a need for a POR circuit where the assertion voltage is independent of VDD ramp-rate, consumes zero or near zero steady-state current, has a low re-arm time, and is suitable for DVFS/DSM applications.